FPGA Engineer

RTL FPGA Design Engineer Experience: 2 to 4 YearsLocation: Hyderabad, India. Job Description:Minimum of 2 years of RTL design and development experience, preferably in a customer facing roleMinimum of 2 years of experience in FPGA Verilog design, technology, and toolsExperience in developing RTL designs in one or more of the following technologies: PCIe, Ethernet, TCP/IP, Packet processing, USB, etc.Proficient in debugging RTL code using simulation tools Excellent ability to analyze and isolate RTL and test bench issuesProficient in using UVM testbenches and working in Linux and Windows environments Experience in HW testing, including working with test equipment, logic and traffic analyzers, test generators, etc.Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Scripting language experience: Perl, Python, Makefile, shell preferred. Experience in C programming is an advantage.

About CompanyACL Digital, part of the ALTEN Group, is a trusted AI-led, Digital & Systems Engineering Partner driving innovation by designing and building intelligent systems across the full technology stack - from chip to cloud. By integrating AI and data-powered solutions, we help enterprises accelerate digital transformation, optimize operations, and achieve scalable business outcomes. Partner with us to turn complexity into clarity and shape the future of your organization.